The basic CMOS logic gate, as its known to those skilled in the art, consumes essentially no or a relatively small amount of power, except when it is actually in a switching state (a change in input causes the output to change). Circuits including CMOS logic gates often comprise a large number of such gates, synchronised to a single clock signal. Synchronous systems are preferred from a design standpoint, and their synchronous behaviour is believed to be well understood by people skilled in the art. All logic gates of such a circuit switch simultaneously, and the load presented to the power source appears as a short, heavy burst, synchronised with the clock. Compensation for this heavy power drain, as a result of current flowing simultaneously into these gates, often necessitates the use of a large supply reservoir capacitor in the power source. This large capacitor is often undesirable.